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AKaga2's avatar
AKaga2
Icon for New Contributor rankNew Contributor
4 years ago

Fatal Qsys error message

Such message I always get each time I tried to generate a Qsys project in my computer: Info: Interconnect is inserted between master pb_dma_to_descriptor_ram.m0 and slave descriptor_memory.s1 beca...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

What is the system component that is failing? There is no info here about it. Is this an IP? How is it parameterized and connected to the rest of your system? The screenshot doesn't show this. More info needed on the component that is actually causing the failure.