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Do You mean, that:
1). power supplies with fast ramp times are more expensive, than with slow ramp times?
2). if FPGA configuration with standard POR is chosen, then the designer can save money using cheaper power supplies with slower ramp times?
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The choice between whether to use fast or slow comes down to how much current can your input supply and how much capacitance do you need to charge on the board.
Where does the relationship between power-on-ramp time come from?
The total charge on a capacitor is Q = CV
If this capacitor is charged via a constant current source, then since I = dQ/dt = CdV/dt, the inrush current onto the capacitor is I = C Vout/Tr, where Tr is the ramp time.
If you make the ramp time longer, you lower the current. Why does that matter? Most connectors and power-sources have current-ratings that you should avoid violating.
How much capacitance is needed? If you needed to power a dense Stratix V device with lots of power rails, there would be lots of power supply bulk capacitance that you would need to change, hence a longer power-on-reset time might be appropriate. If however you were powering a single low-density Cyclone series device, with not too much bulk capacitance, then a fast POR would be fine.
Read through the following to see images of power supply power-on sequences ...
http://www.ovro.caltech.edu/~dwh/wbsddc/power_supply_design.pdf http://www.ovro.caltech.edu/~dwh/wbsddc/power_supply_design.zip and then how to design an entire power supply system
http://www.ovro.caltech.edu/~dwh/wbsddc/ts4_power.pdf Cheers,
Dave
Honored Contributor
