Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThanks for the prompt reply. After some minor cuts and jumpers I disabled JTAG and switched to standard POR. nCONFIG is permanently low (explains why I can program the EPCS, but not the FPGA) despite it being an input and despite a 10k pullup to 3.3V. There's no short to ground on it when power isn't applied. During reset is nCONFIG driven low? The datasheet states that it's an input so I'm having a tough time seeing how/why it's driven low.
After some inspection I discovered that my layout guy forgot about the ground slug on the bottom of the 144 pin package. The datasheet indicates that this is an electrical must. The layout is such that I was able to lift the FPGA, drill a hole (ugly I know) and attach the ground slug to the ground plane. Come monday I'll be able to test it. As a first reaction, does the lack of electrical connectivity on that ground slug seem like a reasonable explanation for the FPGA not leaving reset? Thanks, D