Fast POR AS configuration of Cyclone 3

Altera recommends to connect unused JTAG input pins permanently to inactive levels (TCK to GND, TMS and TDI to VCCIO). Otherwise they should have sufficient low impedance pull-down and pull-up resistors. Particularly TCK without an 1K pull-down is known to be susceptible to interfering signals. However, if the pins are unconnected at the FPGA, I would expect that the FPGA internal resistors can keep them inactive.

I understand, that you have been programming the AS memory successfully, but there's no indication, that the FPGA is comming out of reset at all. So there may be other basic problems, e.g.

- missing or incorrect supply voltages

- missing ground connection of exposed pad

- missing pull-ups at configuration pins