Fast Passive Parallel x32 for Cyclone V and FPGA configuration by the HPS

I am referring to the link below

http://www.altera.com/literature/hb/cyclone-v/cv_54013.pdf

and with respect to this

Chapter 4-6, Table 4-1:Configuration Schemes for FPGA Configuration by the HPS

with respect to this link: http://www.altera.com/support/devices/configuration/schemes/cfg-matrix.html

My question is why is it that in the second link, it indicates FPPx32 by Cyclone V is not supported. But in the first link under table 4-1 shows that it is possible to configure in FPPx32? Why is there this conflict. I need to understand because the second link is consistent with the behavior in Quartus II version 14.0 and 13.1 when I try to create the rbf file, it says the mode is not support.

But then if that is the case, my biggest confusion is when working with the DE1-SoC kit, under the HPS_LED_HEX example, the rbf file is converted from the using FPPx32 compression enabled.

My 2 questions are 1: how do I convert to in FPPx32 from my sof to rbf file with Cyclone 5 device. and 2: how do I enable compression mode. Because there is no option for me to enable compression. The button to click that does not work...

Anyone encountered this issue before?