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Altera_Forum's avatar
Altera_Forum
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14 years ago

Fan out of global clock pin?

Hello,

I wanted to know what is the max fan-out (driving external chip) of

- a glabal clock out pin

- a normal IO pin

I have to design a board where FPGA will have 100 SPI interfaces (32 ADC's, 32 amplifiers etc..).

Each SPI interaface has clock, SDI, SDO etc,

If i use individual clocks () for all 100 chips then i would require a FPGA with bigger no of pins.

Can I use one global clock out pin of FPGA to drive more than 1 clock signal of ADC (for e.g).

Please let me know.

best regards,

VVP

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    There's no difference in available drive strength between dedicated clock outputs and general I/O pins, only a small difference related to delay skew and jitter.

    The question mainly refers to your PCB routing, connected load capacitances and possible termination methods. Connecting 100 SPI slaves isn't impossible but surely restricts reasonable clock frequencies. External clock buffers may be a means to achieve a better signal quality along the SPI chains.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the response.

    I have to use A/D converter for eg:ADS1255/56 (SCLK=10MHz).

    Can I connect "one" FPGA global clock out pin to SCLK's of "8" ADS1255/56 in parallel.

    This would mean "one" FPGA clock out pin (drive strength for eg:12mA) would need to drice SCLK's of "8" ADS1255/56.

    This would reduce pin count significantly.

    How do i find out how many chips a FPGA output pin can drive?

    Please let me know ur suggestion.

    It would be very useful to me.

    Best Regards,

    VVP