Failed to Enumerate Stratix IV GX FPGA Development PCIe Board on PCIe 3.0 Bus

Ritesh,

Normally if you had a kit , there would be some example projects that run in Quartus ... the function is typically captured in a tool , QSYS, that

allows the various IP blocks to be configured ... ie for PCIe , do you want to configure as X1, X4 or X8 lanes and at Gen1, Gen2 or Gen3 speed if supported. The QSYS system can then generate the Verilog or VHDL ( RTL ) . Once you have the RTL, synthesis will run resulting in the .sof file that configures the FPGA elements to perform the design function.

I will look up the Stratix IV kit .pdf's and attach pointers to them.

Best Regards, Bob.