Honored Contributor
Honored ContributorHi, again
The connections between nios and epcs signals are the same as yours, Jens. And those connectios are ok because we proved them by sending .pof file via jtag, previously transformed into .jic file. (with "file->convert programming files" in quartus ) I think this works someway similar to nios2-flash-programmer but for quartus and fpga files instead nios and firmware files. That's to say, it uses the same signals that i am trying (it load the file via jtag and then it is programmed into epcs via data0, dclk, etc). We are going to analyze the signals because, if there isn´t anythig else, the problem can be due to bad pull-ups or something like that, relating with these signal after the fgpa configuration fase. (hardware design is not mine, so i dare not change it if i break something). In other way, i configured the avalon slave clock for the epcs_controlled to 50Mhz (that is my nios frequency). Could it be too fast or is it irrelevant?
