New Contributorhi,
according to F tile, the recover clock can only be derived REFCLK_FGT_8/9_P/N, which are matched with Q2 and Q3; if SFP is going to connecting with Q0, how to connect the recover clock from Q0?
Frequent ContributorHi,
As mentioned in the user guide "When you enable the FGT CDR Output (RX recovered clock output), you must physically map the corresponding FGT PMA to FGT Quad 2 or 3, and you must physically map the FGT CDR Output (RX recovered clock output) to the FGT reference clock location 8 or 9 (configured as output)."
For more info, please refer 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel®...
Thank you,
Kshitij Goel
Frequent ContributorHi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel
