New Contributor
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.
Regards,
Wincent_Altera
New ContributorGood morning.
I'm using "AGF" F-series device because this is the part that is on the development board the SDI example design is running.
As for you second bullet point is that a prerequisite for the transceiver debug toolkit to run? Because I'm only enabling the debugging capabilities in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, which is part of the SDI example design and is connected to the SDI II IP.
The reason we want to run the transceiver debug toolkit is to be able to view the eye of the signal received in Rx. At the moment we don't have an analyzer that supports 12G multi-rate SDI signal and we were hoping that by checking the eye of the signal, when 12G rate is selected, we would be confident that the design is working within the requirements specified by the protocol.
Obviously we've checked it's working with SignalTap and that the Rx is locking at the 12G multirate mode. Just an extra visualization of the signal. If this is not supported then you can close this ticket.
Thank you for all the help.
Regards,
Vasileios Anastasiou.
Regular ContributorHi Vasileios,
I’m glad that your question has been addressed, I now transition this thread to community support. If you have new question, please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of ddesire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.
Regards,
Wincent_Altera
