Execution Time of VHDL code

VHDL is not like a programming language.

The operations it describes are generally not sequential but parallel, since they are implemented in a PLD as combinatiorial logic, physical registers and so on.

These logic elements continuously 'execute' their function at any time: there's not a 'program counter' which activates them sequentially.

Rather than execution time, we speak of timing, and this involved the propagation path of signals between the logic elements of the design.

but, you can reliably work out the latency of a given algorthm.

Knowing the clock speed, and the pipeline delay, you can work out the input to output lacency. You can actually work this out from the VHDL code.

Well one cycle of clock = 1/clock_frequency

So.. you just see how many cycles it takes to do something (algorithms are usually coded as state machines) and voila

Thank you for all of you for this clarification. The problem is resolved by the logic analyser. I use pin as output. At the begining of my program, i affect 1 one logic on the pin after release the program i force the output to 0;

With the logic analyser i measure the delay between 1 and 0.

I hope that is clear.

Thank you very much.:):):)