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Altera_Forum
Honored Contributor
14 years agoVHDL is not like a programming language.
The operations it describes are generally not sequential but parallel, since they are implemented in a PLD as combinatiorial logic, physical registers and so on. These logic elements continuously 'execute' their function at any time: there's not a 'program counter' which activates them sequentially. Rather than execution time, we speak of timing, and this involved the propagation path of signals between the logic elements of the design.