Honored Contributor
Honored ContributorDear Dave,
I have tried to feed the two designs with only one source of clock. But it seems like the RX design did not get a proper input clock from the TX. I tried to test internal loopback at RX and had this error msg when started the monitor process: error: This transaction did not complete in 60 seconds. System Console is giving up. while executing "master_write_32 {/devices/EP4S(100G2|40G2)@1#USB-0/(link)/JTAG/(110:132 v1# 0)/phy_0/master} {0x1000004} {0x00000001}" while executing "master_write_32 $port_id $address $wdata" (procedure "reg_write" line 9) invoked from within "reg_write $GEN_BASE_ADDR $GEN_RANDOMLENGTH 0x00000001 " (procedure "SETGEN_LENGTHRANDOM" line 5) invoked from within "SETGEN_LENGTHRANDOM" (procedure "CONFIG_BURST" line 2) invoked from within "CONFIG_BURST $bursttype $burstsize $pkttype $pktsize " (procedure "CONFIG_TRAFFIC" line 14) invoked from within "CONFIG_TRAFFIC $BURST_TYPE $burst_size $PACKET_TYPE $PACKET_SIZE $MAC_SRC_ADDRESS $MAC_DST_ADDRESS" (procedure "TEST_ALTPMA" line 7) invoked from within "TEST_ALTPMA $TEST_BURST" (procedure "TEST" line 42) invoked from within "TEST ALTPMA 100 1" Do you have an idea of where the error comes from? I just can think that the RX design does not have the synced clock. (Well, the design works well if I use the 100 clock from local generator in board) Briefly, the design needs two input clocks, one is a 644.53 MHz reference clock for 10 Gbps Eth component (that provides a 156.25 MHz clock for PCS block), and the other is a 100 MHz synchronous clock that is the common clock for all the components including System controller, Eth10g, Traffic controller (=traffic generator+traffic monitor). I checked the reference manual and there is a differential SMA clock output (pin J16, J17) from FPGA (pin K34, J34) and a differential SMA clock input (pin J14, J15) to FPGA core pin (AV22, AW22). Therefore, I use a pair of SMA cables to connect (J16, J17) in TX board to (J14, J15) in RX board and assign the 100 input clock in RX design to (AV22, AW22). That way, the RX should have the synced clock with TX. What else I should check? If I need to provide the same reference clock for both TX and Eth10g? I did not do this because the board has only differential SMA clock input to FPGA transceiver but not output one. By the way, I don't really understand the purpose of the word "differential", namely, both clock and transceiver channel have positive and negative components. Can I just use only either positive or negative when I assign pins for designs? Please help to answer. This is the reference manual for me board: http://www.altera.com/literature/manual/rm_sivgt_si_dev_board.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=stratix%20iv%20gt%20signal%20integrity --- Quote Start --- 5) The high-speed transceiver links will start in lock-to-reference, and then transition to lock-to-data mode. Since the data source and sink PLLs are locked to the same reference, you won't see any clock drift. --- Quote End --- Regarding this, did you mean the RX Eth10 component first use the local reference clock and then it extracts clock from receiving data? And how can I check or implement this? Thank you very much.
