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Look at your board schematics.
1) Is there an clock output on an SMA connector? Eg., from an FPGA clock pin or from an on-board oscillator fanout buffer?
2) Is there a clock input on an SMA connector?
3) Connect board#1 -> board# 2 with an SMA cable from the clock output SMA to the clock input SMA.
4) The design on the board#1 (with the SMA clock output) should use an FPGA pin with the same clock as the output clock. The design on the board#2 (with the SMA clock input) should use the SMA input clock as the reference. Now both boards are synchronous.
5) The high-speed transceiver links will start in lock-to-reference, and then transition to lock-to-data mode. Since the data source and sink PLLs are locked to the same reference, you won't see any clock drift.
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Great advice! exactly what I am looking for. I think this will really helps. I will try this weekend and update the result then.
Thanks a lot.
Honored Contributor
