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If one board uses a 156.25MHz reference that is actually a few kHz high, and the other board uses a reference that is a few kHz low, then one board will send data to the other
faster than ideal. The clock-and-data recovery (CDR) in the receiver will track the higher frequency, however, if you use a FIFO to cross clock domains between the recovered clock and the local clock, you will eventually get a FIFO overrun (or underrun in the case of a slower transmitter). Protocols like 10G take care of this by having protocol codes that can be added or deleted. If you are implementing FPGA-to-FPGA communications, then the system becomes simpler if you use a
synchronous reference. You can implement this reference using an external synthesizer and send a copy of the signal to each board, or you can use one of your boards as the clock source and the other can receive a clock from the first, and use it for clocking its receiver logic.
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Dear Dave,
How can I implement the synchronous reference clock? If you can provide some more details regarding the external synthesizer such as examples, materials,...I am thinking this is the problem for the board-to-board communication I am encountering now.
Thanks
Honored Contributor
