Example designs for communicating two Altera boards

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I have installed Q II 11.1 SP1, exactly the Build 216 11/23/2011 SJ Full Version. Unfortunately, no change was made in the process of generating any designs that include a On-Chip Memory IP core. The latest one I tried was the JTAG-to-Avalon-MM tutorial you suggested. Hence, I attach here so that you can check whether the issue is coming from the design itself or it is not possible to use On-chip memory cores in Qsys/SOPC Builder in my system (Windows Server 2008).

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Here's what I did:

1) Unzip your design

2) Opened the Qsys design and generated the system

3) Clicked on the files tab in the main GUI, and then clicked on the qsys_system.qsys and set it as the top-level entity (as described in the tutorial).

4) Synthesized the design.

There were no errors.

What was the problem you saw?

If you think its a problem with Windows Server 2008, download VirtualBox, install Windows or Linux into that, and then install the Quartus tool there.

Note that Windows Server 2008 is not a supported OS:

http://www.altera.com/download/os-support/oss-index.html

If you're serious about FPGA design, then you should install a supported OS.

Cheers,

Dave