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Altera_Forum
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14 years ago

Example designs for communicating two Altera boards

I am looking for example designs or tutorials showing how to communicate two Altera boards using simple protocols. The purpose is to see how the two devices interact by transmitting data back and for...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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always the generation process hangs with the message "Starting classic module elaboration" in the step of "creating HDL design files for senthesis". I am using Quartus 11.0 and 11.1 and the error occurs whenever the design has On-chip memory core. If you can help to check this or give me a clue to fix the error. Sorry for putting this here:)

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Try 11.1sp1. The tutorial was tested under Windows XP and 7, Linux Centos 6.2 and Ubuntu 11.10. There were no problems with that version of Quartus.

Cheers,

Dave