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Yes, this is my plan. However, there is not available example for 10GBASE-R, and I am trying to create generator/checker component with XGMII data width instead of using the existing Avalon ST gen/checker. So, I need to write the component in verilog and then add them to Qsys library.
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That sounds like a good plan.
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Once I have those, I can create the complete design that includes the 10GBASE-R, the generator/checker. The JTAG to Avalon Master Bridge has a master interface to control the three components so that I can run design on devices and use XCVR Toolkit to test the signal quality. If you have any suggestion/comment about this intention?
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Here's a tutorial that shows you how to use the JTAG-to-Avalon-MM master component and Avalon-MM BFM components:
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial --- Quote Start ---
>> Use of an external PHY
Frankly, I have not considered this. Can you put some more details as it looks very important.
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If your design fits in a Cyclone or Arria series device that has transceivers that operate to 3.125Gbps with a XAUI interface that uses 8/10B encoding, then you can interface to an external PHY (I think Vitesse has some) that will decode-and-reencode the data as 10.3125Gbps SFP+ (with 64/66B encoding). A lower-cost FPGA plus external PHY may be more cost effective than using a high-end FPGA.
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Regarding to the resources of my boards and devices, I also wonder that in case I need memory to store data for board-to-board communication application, which kind of memory I can use? As far as I understand, both the on-chip memory (TriMatrix memory includes 640-bit MLABs, 9-Kbit M9K, and 144-Kbit M144K blocks) and on-board memory (64-MB synchronous flash) are quite limited. Is it possible for my board to use external memory and if yes, how to do so as I do not see this infos in the reference manual. Can you please help to confirm my understanding and give me some explanation also?
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Only you can answer this question. It depends on what you have to store. If you are only testing, then you can use a PRBS generator to create a lot of random data.
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Unfortunately, I cannot change my devices (I am not the one who decides). I need to do everything with these boards.
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You can develop with the boards you have, however, someone should see whether this is appropriate for the final application. It will not change the logic you develop, since that MAC logic is probably identical.
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And how can I check the amount of resource used for PCS only? As I know the compilation report provides the summary for whole design rather than each sublayer.
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The hierarchy window can be used to show how much each block in the design uses. You just need to realize its there - use the horizontal scroll bar and you'll see it displayed after place-and-route.
Cheers,
Dave
Honored Contributor
