Example designs for communicating two Altera boards

Dear Dave,

Once again, thank you very much for your very useful advice.

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My recommendation would be to take the XCVR debug example, which works, and simulate it. That'll allow you to probe a working design.

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Yes, this is my plan. However, there is not available example for 10GBASE-R, and I am trying to create generator/checker component with XGMII data width instead of using the existing Avalon ST gen/checker. So, I need to write the component in verilog and then add them to Qsys library. Once I have those, I can create the complete design that includes the 10GBASE-R, the generator/checker. The JTAG to Avalon Master Bridge has a master interface to control the three components so that I can run design on devices and use XCVR Toolkit to test the signal quality. If you have any suggestion/comment about this intention?

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I assume this is the 10GBASE-R IP you are looking at:

http://www.altera.com/products/ip/iup/ethernet/m-alt-10gbase-r-pcs.html

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Yes, exactly the document I have studied. I also refer to a hardware demonstration in http://www.alterawiki.com/wiki/10g_ethernet_and_10g_base_r_phy_interoperability_hardware_demonstration_design

Actually, this works with different board and I changed the pin assignment for my device. But I got some errors during recompilation. I will fix this next days. Do you suggest other materials or design examples?

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You should synthesize to see how much logic the PCS layer is using. Given that the Stratix IV GT might not be a good use of resources, have you considered using a GX device with an external PHY?

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Frankly, I have not considered this. Can you put some more details as it looks very important. Regarding to the resources of my boards and devices, I also wonder that in case I need memory to store data for board-to-board communication application, which kind of memory I can use? As far as I understand, both the on-chip memory (TriMatrix memory includes 640-bit MLABs, 9-Kbit M9K, and 144-Kbit M144K blocks) and on-board memory (64-MB synchronous flash) are quite limited. Is it possible for my board to use external memory and if yes, how to do so as I do not see this infos in the reference manual. Can you please help to confirm my understanding and give me some explanation also?

Unfortunately, I cannot change my devices (I am not the one who decides). I need to do everything with these boards.

And how can I check the amount of resource used for PCS only? As I know the compilation report provides the summary for whole design rather than each sublayer.

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What you really should be doing then is getting the PHY working in the simulator so that you can simulate while working on your custom logic.

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I will try to do this next days. I see the importance of this step. Thank you very much for this timely advice.

Best,

PLMT