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I am going to build a 10Gbps Ethernet Passive Optical Network (EPON) system where one FPGA will play a role as a center office device (OLT) and several other FPGAs will be customer premises (ONU). The boards will interface SFP+ modules. The design will consist of a physical layer protocol (probably by using Altera 10GBASE-R IP core) and my own implementation of MAC protocol (probably by modifying Altera 10GbE MAC IP core). The MAC for OLT device is different from that for ONUs.
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Ok, thanks for the description.
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Therefore, I am trying to have physical layer first. I studied the Altera XCVR PHY IP Core User Guide and XCVR Architecture in Stratix IV manual. Then I tested the provided On-chip XCVR debugging examples in harware (not yet in Modelsim). However, 10GBASE-R is provided by Altera without a similar example for testing in hardware, so I tried to create that in Qsys with Avalon ultilities. With some knowledge from reading specs and Qsys, I though/hoped that I would create a complete 10GBASE-R design, then simulate it in Modelsim as well as test it on harware.
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My recommendation would be to take the XCVR debug example, which works, and simulate it. That'll allow you to probe a working design.
I assume this is the 10GBASE-R IP you are looking at:
http://www.altera.com/products/ip/iup/ethernet/m-alt-10gbase-r-pcs.html Note that 64/66B encoding is not supported in the Stratix IV hard-IP PCS, so it gets implemented in the fabric. You should synthesize to see how much logic the PCS layer is using. Given that the Stratix IV GT might not be a good use of resources, have you considered using a GX device with an external PHY?
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I hoped that this top-down approach would help me understand the overview of my design more quickly.
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It might, if you also know how to simulate Qsys and create custom components. However, if you're introducing lots of new concepts, then you might actually be making the design more complicated.
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Moreover, as the PHY layer is provided as IP core, I do not really want to spend much time for this. I just want to know how to test this in hardware and know how to interface this with the other components in my final design. The major part of my project is to design the customized MAC sublayer. That is why I am doing things in reverse.
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What you really should be doing then is getting the PHY working in the simulator so that you can simulate while working on your custom logic.
Cheers,
Dave
Honored Contributor
