Example designs for communicating two Altera boards

Many thanks to Dave and please find my answers as following:

1-What are you looking to test? The transceivers?

Yes, the main purpose is to to test transceivers, in particular with the Altera PHY IP cores. But besides these, I want to know how to create a design for two boards to communicate one another using some simpler protocol than the PHY IP cores. The data rate can be any not greater than 11.3Gbps

2-What have you tried so far?

I have tried to test XCVR with On-chip debugging design examples provided by Altera. Then I created similar designs with Lowlatency and Custom PHY for various data rates using Qsys. However, I would like to have a 10Gbase-r PHY design and I could not create this in Qsys. I don't know if it is possible to create such design by using available components in Qsys.

3-Do you know how to configure the ALTGX and ALGX_RECONFIG components?

I have general idea about the ALTGX and ALTGX_RECONFIG but have not ever used these as I want to try designing with Qsys first.

4-What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards?

I have SMA cables for physical connection between the two boards. For a synthesizer to provide the common clock, if you can make this clearer?

Thanks.