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Hello,
I synthesized my design in Quartus II , "EDA Netlist Writer" and I keep getting the following message:
"Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script".
The problem is that the Bank 1 GCLK, in MAX2, EPM2210F256I5 (meant to be enable for clock) in not going up to 3.3V ('1').
what should I do, can anybody help?
Regards,
Idan
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Hi,
I think the warning is not related to your problem. The warning occurs, because the default setting of Quartus switched on the so-called EDA Netlist writer. The writer is used
for generation of a netlist of your design for third party EDA tools like simulation tools.
Kind regards
GPK
Honored Contributor
