Altera_ForumHonored Contributor10 years agoError using while converting code to VHDL Dear All, I am trying to find delay between two signals using cross correlation on FPGA .Kindly can some one please help me how i can do that. Any link or any useful informati...Show MoreUntitled5.m0 KB
Altera_ForumHonored Contributor10 years agoThe HDL Coder does not tell you anything more? What is connected to port 1?
Recent DiscussionsLTC Connector DE10-Standard FPGAIssue with configuring EPCQ64A & CycloneAgilex5 A5EB013BB23BE4S BSDLMAX 10 FPGA Programming Failure via JTAG – nSTATUS & CONFIG_DONE as No ConnectASx4 Interface debug in MSEL=111 (JTAG mode)