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Altera_Forum
Honored Contributor
13 years agoError: Type conversion (to UNSIGNED) can not have string literal operand
Hai all, I have run a testbench simulation in ModelSim and get this error: # ** Error: bmp_generator.vhd(401): Type conversion (to UNSIGNED) can not have string literal operand.# ** Error: ...
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- I have another question, can you help me to verify it. I have line code of bp<=SXT(a,9) + b and bp<= a+b, wheres a and b is std_logic_vector(7 downto 0) and bp is std_logic_vector(8 downto 0). My question is what the different between the two line codes? thanks in advance --- Quote End --- Neither is correct. If a, b, and bp are all std_logic_vector, then you cannot add without converting to signed or unsigned. std_logic_vector is just an array of bits, the compiler does not know how you want to interpret those bits, so you have to tell it using explicit casts/type-conversions.
bp <= std_logic_vector(unsigned(a) + unsigned(b));
where a and b are converted to unsigned, the sum a+b is also unsigned (1-bit wider), and it is converted to std_logic_vector before being assigned to bp (which is also std_logic_vector). Cheers, Dave