Error SOPC : "the sink has empty signal of 2 bits but the source does not"

What version of the tools are you using? The VIP does not support the "empty" signal of the avalon streaming interface. Is there a reason to put a FIFO between the frame buffer and the color plane sequencer? The frame buffer really acts like a very large FIFO anyway?

Jake

Thanks, you were right I removed it. But then I had clock compatibility problems and I put everything, including the clocked video output, to ddr_sdram_sysclk. I have problems with NIOS II so I haven't check yet but do you think it will be a problem ?

I have a cyclone III C25 and am using quartus II 9.0sp1

Myriam

I also got this questionable error. refering to the first error "alt_vip_vfb_0.dout/fifo_0.in". The fifo actually doesn't have any empty sink input in generated VHDL. I manually added one empty_out to the my source interface, and SOPC didn't give any error any more, instead reported "Warning: suspicious signal of [module_name]_avalon_streaming_source_empty' at system top level", then create an output at top level.... not some severe problem, but uncomfortable.

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Hello,

I am working with the VIP suite and I have an error in SoPC builder between the frame buffer and the fifo and between the fifo and the color plane sequencer.

Error : alt_vip_vfb_0.dout/fifo_0.in : The sink has a empty signal of 2 bits, but the sink does not.

Error : fifo_0.out/alt_vip_cpr_0.din0 : The sink has a empty signal of 2 bits, but the sink does not.

What should I do to ?

Thanks,

Myriam

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We were using TSE MAC and we got similar error.

To rectify, just edit properties of TSE MAC and make sure that FIFO width is correct (8 bit/32 bits)