Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI also got this questionable error. refering to the first error "alt_vip_vfb_0.dout/fifo_0.in". The fifo actually doesn't have any empty sink input in generated VHDL. I manually added one empty_out to the my source interface, and SOPC didn't give any error any more, instead reported "Warning: suspicious signal of [module_name]_avalon_streaming_source_empty' at system top level", then create an output at top level.... not some severe problem, but uncomfortable.
--- Quote Start --- Hello, I am working with the VIP suite and I have an error in SoPC builder between the frame buffer and the fifo and between the fifo and the color plane sequencer. Error : alt_vip_vfb_0.dout/fifo_0.in : The sink has a empty signal of 2 bits, but the sink does not. Error : fifo_0.out/alt_vip_cpr_0.din0 : The sink has a empty signal of 2 bits, but the sink does not. What should I do to ? Thanks, Myriam --- Quote End ---