Honored ContributorHello,
I have an error that i don' t understand. Something, do you can to help me ? PORT "IO" DOES NOT EXIST IN PRimitive "AND4' of instance "I_36_30" thank's in advance. Olivier
Honored ContributorAre you writing RTL at primitive level?
AND4 is an altera's logic primitive. It has one output (OUT) and 4 inputs (IN1, IN2, IN3, IN4). It seems like you u have named a module AND4. Try to change its name. http://quartushelp.altera.com/9.1/mergedprojects/hdl/prim/prim_file_and.htmHonored Contributorok it's good
