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Altera_Forum's avatar
Altera_Forum
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17 years ago

error in compiling VHDL CODE

sir, i'm using modelsim for simulating my VHDL code.

When i was simulating, i encountered an error. The error statement was as given below:

Signal "prior_a0" is type ieee.std_logic_1164.std_logic; expecting type ieee.std_logic_1164.std_logic_vector

can u pls help me in trobleshooting this problem..

i'm stuct in between my project because of this error.

kind:)y answer

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hey varun first define this signal, lead_user_output;

    (I could not found this in ur code)

    And also take care of its size,

    U should assign this signal to a signal of same size only...........
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hai, sir.....

    i hav declared lead_users_output as signal

    thank u..............
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hello, sir i hav another problem ...

    i need xilinxcorelib.....i'm using modelsim and i need xilinxcorelib to map this library onto my modelsim.

    where can i download xilinxcorelib