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Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Error fitter for PHY IP gen3

Hi All, I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, gen3 configuration.(Single lane) the fitter reports the following error: Error (15653): The Fitter cannot find ...
  • Deshi_Intel's avatar
    Deshi_Intel
    5 years ago

    HI,


    You are right. Your FPGA pin assignment setting is fine.


    The problem is on your top level design connection. Below is the fix I made to your vqm design

    1. Fixed broken NativePHY (tx_serial_data) connection
    • I presume you want to connect to output port "DIFF100_PCIE_MOLEX_1KU12_PET" so I connect it back
    1. Fixed wrong clocking connection to NativePHY for PIPE GEN 3
    • fPLL tx_serial_clk should be connected to NativepHY tx_serial_clk0
      • ATX PLL tx_serial_clk should be connected to NativepHY tx_serial_clk1


    You can also generate the example design directly from NativePHY IP to learn about the design connection

    • Goto NativePHY -> design example tab
      • change the fPLL default frequency from 125MHz back to 100MHz
      • Then click generate example design button


    Thanks.


    Regards,

    dlim


Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
5 years ago

Hi dlim,

thanks for your replay, I remove all the project and compile only the 4 IP

I add the .qar file ( please look for v2 )

( I want to mention that I succeed to compile PHY IP with gen1 AND gen2 with the same pins and constraints )

Thank you!

Moti