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Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Error fitter for PHY IP gen3

Hi All, I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, gen3 configuration.(Single lane) the fitter reports the following error: Error (15653): The Fitter cannot find ...
  • Deshi_Intel's avatar
    Deshi_Intel
    5 years ago

    HI,


    You are right. Your FPGA pin assignment setting is fine.


    The problem is on your top level design connection. Below is the fix I made to your vqm design

    1. Fixed broken NativePHY (tx_serial_data) connection
    • I presume you want to connect to output port "DIFF100_PCIE_MOLEX_1KU12_PET" so I connect it back
    1. Fixed wrong clocking connection to NativePHY for PIPE GEN 3
    • fPLL tx_serial_clk should be connected to NativepHY tx_serial_clk0
      • ATX PLL tx_serial_clk should be connected to NativepHY tx_serial_clk1


    You can also generate the example design directly from NativePHY IP to learn about the design connection

    • Goto NativePHY -> design example tab
      • change the fPLL default frequency from 125MHz back to 100MHz
      • Then click generate example design button


    Thanks.


    Regards,

    dlim


Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


From the fitter error message, looks like it's complaining you are either using outdated Intel FPGA IP core or there is some invalid setting issue that caused fitter error later.


Typically Quartus fitter compilation error is either caused by wrong IP setting, wrong Quartus project top level design connection or wrong FPGA pin placement and pin setting issue.


Pls remove all sensitive FPGA core user design logic and just maintain the simplify design that just contains top level design with 4 Intel FPGA IP core that able to duplicate the fitter error.


Share your Quartus archived project *.qar then I can help to review your design to debug fitter error


Thanks.


Regards,

dlim