Altera_ForumHonored Contributor16 years agoError due to always enabled I/O buffer Hi all, I had generated a SOPC system using sdram controller, jtag, 2 pio and nios. When I compile the design, it shows error as shown below: *************************** Error: The node ...Show More
Altera_ForumHonored Contributor16 years agoCould you please tell me the way to solve this kind of problem in detail.thank you!
Recent DiscussionsThermal Resistance for 10M16SCU324A7GIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAAgilex 3 VCCLSENSE and GNDSENSEAgilex 7 JTAG Config Fails at 1% on Board #2 (Error 18950 / CONF_DONE Low) - But Board #1 WorksEPCQL512 and Remote Update IP ARRIA 10