Altera_ForumHonored Contributor16 years agoError due to always enabled I/O buffer Hi all, I had generated a SOPC system using sdram controller, jtag, 2 pio and nios. When I compile the design, it shows error as shown below: *************************** Error: The node ...Show More
Altera_ForumHonored Contributor15 years agoCould you please tell me the way to solve this kind of problem in detail.thank you!
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information