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Altera_Forum
Honored Contributor
Honored ContributorError: CONF_DONE failed to go high in device 1.
Before anyone comments on this, I have searched the forum and read everything I have found on the internet with people getting this error message. :)
I'll try to post as much relevant information as possible, so the next one who has this problem might get off a bit easier. "Error (209014): CONF_DONE failed to go high in device 1" The error message happens both when trying to program the Serial Flash Loader and when trying to program JTAG directly. The programming fails before there is any progress, it doesn't even say 0%. Auto Detect Device functions as it should though. I get the choice between EP4CE15 and EP3C16, but that has never been a problem with other designs. I have made a custom board with a FBGA256 Cyclone IV EP4CE15 fpga and some peripherals. The fpga is hooked up with JTAG for Serial Flash Loader (SFL) as described in the Device Handbook on page 218 (figure 8-29, revision november 2011). I'm using a 20MHz CMOS oscillator, although that shouldn't have any impact on this issue as far as I know. The supply voltages are derived through separate low-noise, high PSRR LDO-regulators which can deliver max 150mA each. They are connected as such: VCCIO of all IO-bank is 3,3V. VCCINT and VCCD_PLL is 1,2V. VCCA is 2,5V nCE (J3) is connected to ground. nStatus (F4), nConfig (H5) and CONF_DONE (H14) are all pulled to VCCIO by 10k resistors. MSEL are connected as MSEL0(H13)=2,5V, MSEL1(H12)=GND, MSEL2(G12)=GND. But since I'm using JTAG these would be overridden anyways. The JTAG plug is connected as such: 1 - TCK (pin H3), pulled to GND by 1k 2 - GND 3 - TDO (pin J4) 4 - 2,5V 5 - TMS (pin J5), pulled to VCCIO by 10k.# modded this to VCCA. 6, 7,8 - N.C. 9 - TDI (pin H4), pulled to VCCIO by 10k.# modded this to VCCA. 10 - GND Does anyone know anything I can try?37 Replies
Altera_ForumI have tried checking the JTAG signals with a scope. While I haven't done a very thorough check of the signals against spec it does seem to be some activity on all the lines.
- Altera_Forum
Things I have noticed:
1. DEV_OE and INIT_DONE are each connected to a LED to ground with 470ohm resistors. They light up for a moment when I click the program-button in the Device Programmer. They both give 3,3V. - When INIT_DONE lights up, this should mean that the FPGA has entered "User Mode". But what does it mean when it goes high for a moment and then low again? Might this be the registers initializing to a high value or something like that before configuration? More things I have tried: 2. Checking the box for Compressed Bitstream. No effect. 3. Enabling device-wide output enable (DEV_OE) and reset (DEV_CLRn) as per suggestions in another thread. No effect. 4. Disconnecting the LEDs on DEV_OE and INIT_DONE, suspecting they'd overload the output. No effect. - Altera_Forum
Does anyone have a suggestion?
Edit: I have manufactured a new board, but the same error is still persisting. I have tried disconnecting the 2,5V from pin 6 on the jtag-plug. That had no effect either. - Altera_Forum
I have probed the JTAG signals (see pictures below).
Is this normal waveform? This pattern repeats itself for a little while when I press the program-button, and then nothing. https://www.alteraforum.com/forum/attachment.php?attachmentid=6714 TCK https://www.alteraforum.com/forum/attachment.php?attachmentid=6715 TDI https://www.alteraforum.com/forum/attachment.php?attachmentid=6716 TDO - Altera_Forum--- Quote Start --- VCCD_PLL and VCCA is 2,5V ... The JTAG plug is connected as such: ... 4 - 2,5V --- Quote End --- Please, check your schematic. - VCCD_PLL must be 1.2V for Cyclone IV (handbook, vol.1, chap.11, page 2) - JTAG pin 4 is a target VCCIO (3.3V in your case) - JTAG pin 6 (nCS) is an output from JTAG, leave it unconnected.
- Altera_Forum--- Quote Start --- Please, check your schematic. - VCCD_PLL must be 1.2V for Cyclone IV (handbook, vol.1, chap.11, page 2) --- Quote End --- I'm sorry. That was a typo. It is connected to 1.2V. --- Quote Start --- Please, check your schematic. - JTAG pin 4 is a target VCCIO (3.3V in your case) --- Quote End --- Are you sure? The Device Handbook says to use 2,5V as far as I can comprehend. And in the figure (fig. 8-29) pin 4 is connected to VCCA (which is 2,5V), unfortunately. The Device Handbook says the following about the pin: " Power up the VCC of the EthernetBlaster, ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V VCCA supply. Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide." --- Quote Start --- Please, check your schematic. - JTAG pin 6 (nCS) is an output from JTAG, leave it unconnected. --- Quote End --- Yes, I've realized that mistake. I have disconnected it, but I forgot to post it. Edit: I've tried using 1k pull-up on CONF_DONE as well. That had no effect either. The pesky pin holds low anyways. Edit 2: While I was reading the Device Handbook again to check up on the 2,5V on pin 4 I came to notice that I have pulled TMS and TDI to VCCIO(3,3V) instead of VCCA(2,5V). I will try to mod this ASAP.
- Altera_Forum--- Quote Start --- While I was reading the Device Handbook again to check up on the 2,5V on pin 4 I came to notice that I have pulled TMS and TDI to VCCIO(3,3V) instead of VCCA(2,5V). I will try to mod this ASAP. --- Quote End --- This had no effect unfortunately.
- Altera_Forum
Ok. So you can auto-detect your FPGA, CONF_DONE toggless and pll voltage is ok. Can you now check fpga supply voltages with oscilloscope at the rising edge of conf_done?
- Altera_Forum--- Quote Start --- Ok. So you can auto-detect your FPGA, CONF_DONE toggless and pll voltage is ok. Can you now check fpga supply voltages with oscilloscope at the rising edge of conf_done? --- Quote End --- No, CONF_DONE never toggles. It just stays low from start up. I have checked the supply voltages to verify that they don't dip or anything like that. So that part should be OK. Edit: According to this app note it would seem that the FPGA is in Configuration Mode. I don't know if that has any implications though.. http://www.altera.com/literature/hb/cfg/cfg_cf51001.pdf
- Altera_Forum
Hi there,
I think the JTAG I/F should be ok regards voltages and pulls as otherwise the programmer would state a "device not found" or similar message. Additionally you can (or most likely already did) use the "Auto detect" function to check the JTAG itself. If there is anything wrong with the JTAG, the device would not be found at all. Next is (in my opinion) to check, that you have not (unintended) activated the "enablel user supplied start up clock" option (settings => device => device and pin options => General). And even while it may be really stupid to ask this - the target device selected in quartus matches the Cyclone on Hardware? Are there any external Watchdog devices installed that should be "served" to prevent them to reset the FPGA (and if so - is there the required code in the file?) In my opinion (assuming the JTAG I/F is working) this sounds more like some mismatch between the configured device and the hardware... Best regards
