error: can't defined "/" operator

Hello everyone,

Here is my code where I want to add two values of a vector. For example, I have a vector (3,4) and I want to do like this;

(3+4)/2;

Package my_data_types is

Type vector is array (1 downto 0) of integer;

Type vector_next is array (0 downto 0) of integer;

End my_data_types;

LIBRARY ieee;

USE ieee.ALL;

USE work.my_data_types.all;

ENTITY adddiv IS

PORT (

Ra : IN vector;

clk : IN bit;

A : OUT vector_next

);

END adddiv;

ARCHITECTURE adddiv OF adddiv IS

BEGIN

Process(clk)

variable temp: vector_next;

BEGIN

If clk'event and clk = '1' Then

temp := ((Ra(0) + Ra(1))/2);

End if;

A <= temp(0 downto 0) after 20ns;

END PROCESS;

END adddiv;

But, this error occur:

Error (10327): VHDL error at adddiv.vhd(24): can't determine definition of operator ""/"" -- found 0 possible definitions

Can anyone help me..many thanks