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Altera_Forum
Honored Contributor
Honored ContributorError 275062
Hello, My design is a schematic entry utilizing a top level .bdf file consisting of a symbol of a lower level .bdf. The lower level .bdf file consists of symbolized .bdf subcircuits connected wi...
Altera_ForumHonored Contributor
Honored ContributorIm sorry if this may be offensive, but the only people I have seen do schematic entry have been "oldschool", and refused to change. The designs that were passed to me were terrible and very difficult to debug, but this is most likely lack of documentation and the very poor way the blocks were connected back and forth across the schematics. I have also seen equally bad HDL.
I assure you that the market outside the altera forum is very large, and the schematic entry community is miniscule. Job prospects for schematic entry people are rather poor (for FPGA designers).
