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Honored ContributorError 10822?
HI ALL,I just wrote a vhdl program.When i compiled it in QuartusII,it gave me some error 10822:"Error (10822): HDL error at aichselect.vhd(63): couldn't implement registers for assignments on this clock edge".I don't know how to fix it,pls help me!
------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ENTITY aichselect IS GENERIC( ys_time: positive:= 5 ); PORT ( fclk : IN STD_LOGIC; --ϵͳʱÖÓ clk : IN STD_LOGIC; --ÑÓʱʱÖÓ rst : IN STD_LOGIC; enable : IN STD_LOGIC; --ʹÄÜÐźŠadc_end : IN STD_LOGIC; sai0_n : OUT STD_LOGIC; sai1_n : OUT STD_LOGIC; sai2_n : OUT STD_LOGIC; aichok : OUT STD_LOGIC ); END ENTITY; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ARCHITECTURE behav OF aichselect IS SIGNAL count : INTEGER RANGE 0 TO 19 ; SIGNAL saiout : STD_LOGIC; TYPE sai_status IS(st0, st1, st2, st3, st4, st5, st6, st7 ); SIGNAL sai_current_state: sai_status; SIGNAL sai_next_state: sai_status; BEGIN ------------------------------------------------------------------------------ --------------------------------AIͨµÀÇл»×´Ì¬»ú------------------------------ ------------------------------------------------------------------------------ SAI:PROCESS( enable,sai_current_state, sai_next_state ) BEGIN IF(rst = '1' ) THEN sai_next_state <= st0; ELSE CASE sai_current_state IS WHEN st0 => sai0_n <= '1'; sai1_n <= '1'; sai2_n <= '1'; aichok <= '0'; IF(enable = '1') THEN sai_next_state <= st1; ELSE sai_next_state <= st0; END IF; WHEN st1 => sai0_n <= '0'; sai1_n <= '1'; sai2_n <= '1'; aichok <= '0'; sai_next_state <= st2; WHEN st2 => sai0_n <= '0'; sai1_n <= '1'; sai2_n <= '1'; aichok <= '0'; if(rising_edge(clk)) thenif(enable = '1') then
if( count = ys_time) then
count <= 0;
sai_next_state <= st3;
else
count <= count + 1;
sai_next_state <= st2;
end if;
end if;
end if; WHEN st3 => sai0_n <= '0'; sai1_n <= '1'; sai2_n <= '1'; aichok <= '1'; IF(adc_end = '1') THEN sai_next_state <= st4; ELSE sai_next_state <= st3; END IF; WHEN st4 => sai0_n <= '1'; sai1_n <= '0'; sai2_n <= '1'; aichok <= '0'; IF( clk'event AND clk = '1') THEN IF( count = ys_time) THEN count <= 0; sai_next_state <= st5; ELSE count <= count + 1; sai_next_state <= st4; END IF; ELSE NULL; END IF; WHEN st5 => sai0_n <= '1'; sai1_n <= '0'; sai2_n <= '1'; aichok <= '1'; IF(adc_end = '1') THEN sai_next_state <= st6; ELSE sai_next_state <= st5; END IF; WHEN st6 => sai0_n <= '1'; sai1_n <= '1'; sai2_n <= '0'; aichok <= '0'; IF( clk'event AND clk = '1') THEN IF( count = ys_time) THEN count <= 0; sai_next_state <= st7; ELSE count <= count + 1; sai_next_state <= st6; END IF; ELSE NULL; END IF; WHEN st7 => sai0_n <= '1'; sai1_n <= '1'; sai2_n <= '0'; aichok <= '1'; IF(adc_end = '1') THEN sai_next_state <= st0; ELSE sai_next_state <= st7; END IF; WHEN OTHERS => sai_next_state <= st0; END CASE; END IF; END PROCESS SAI; ------------------------------------------------------------------------------ ---------------------------------״̬»úʱÐòµç·------------------------------- ------------------------------------------------------------------------------ STATE:PROCESS( fclk ) BEGIN IF( fclk'event AND fclk = '1') THEN sai_current_state <= sai_next_state; END IF; END PROCESS STATE; END behav;
