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Altera_Forum
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18 years ago

Error 10822?

HI ALL,I just wrote a vhdl program.When i compiled it in QuartusII,it gave me some error 10822:"Error (10822): HDL error at aichselect.vhd(63): couldn't implement registers for assignments on this cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

basically you shouldn't try to implement a clock synchronous construct within a case structure. If the compiler possibly accepts it, it would end up in a gated clock. Apparently he doesn't, may be for additional reasons I didn't yet see.

The rising_edge(clk) should always be the outermost condition in a process, only accompanied by an asynchronous reset condition if applicable.

Regards,

Frank