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We both know that. I wanted you to post the code so I could confirm it was valid VHDL.
The RTL viewer is a Quartus tool, so no, you cannot view the testbench using RTL viewer. Viewing a testbench makes no sense, given that most of the logic does not create RTL. Testbenches contain non-synthesizeable constructs.
I haven't seen that one before. How are you trying to simulate in Modelsim - using Nativelink or from within Modelsim directly?
Cheers,
Dave
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"I haven't seen that one before. How are you trying to simulate in Modelsim - using Nativelink or from within Modelsim directly?"
- I am running it straight from within Modelsim.
Cheers
Honored Contributor
