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- Altera_Forum
Honored Contributor
Please post the problem code.
Hi folks,
While coding in VHDL i am facing this error, in a module using s_sys which std_logic_vector (1 downto 0) i am making decision to assign timing to different signals...because of this error i could not proceed further...can anyone help me out in this.... Thanks..Arun12Please post the problem code.