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AFera1's avatar
AFera1
Icon for New Contributor rankNew Contributor
6 years ago

Error 10170: HDL error. I don't know why it is telling me near text: "="; expecting ".", If someone can help that would be great

module bcd_seven_seg(SW,HEX0,HEX1,Hex2,LEDG); input [9:0] SW; output [6:0] HEX0, HEX1, HEX2; output [9:0] LEDG; wire [6:0] hex0,hex1,hex2; HEX0 = ~hex0; HEX1 = ~hex1; HEX2 = ~hex2; ...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
6 years ago

1) Verilog is a case sensitive language. Check your first module header: Hex2 ==> HEX2

2) lines 6-8 need a type declaration, like (probably) 'wire'. Ie: wire HEX0 = ~hex0; etc

3) (minor) line 11 first arg is only 2 bits wide but function wants 4 bits. Change to: bcd_seven_seg_behavioral u2({2'b00,SW[9:8]},HEX2); to eliminate the warning.