EPCS4SI8N > EPCQ4ASI8N For Old Cyclone FPGA

Hi Mark and Anand,

I have just found out the following part associated with the actual problem in the mentioned AN822 spec:

The dummy clock requirement of the fast read (0Bh) and extended quad input fast read (EBh) commands:

EPCQ—the dummy clock is configurable with the non-volatile configuration register (NVCR). When the EPCQ is used with a Cyclone® V, Arria® V or Stratix® V device, the dummy clock is configured to be 4, 10 or 12, depending on the byte-addressing mode and ASx1 or ASx4 configuration. However, in EPCQA devices, the dummy clock is fixed at 8 and 6 for fast read and extended quad input fast read respectively. Therefore you must regenerate the programming files, such as .pof, .jic, and .rpd.

For further information: AN822 spec, 1.1 Migration Considerations, Operation Commands.

Regards,

Martin