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Honored ContributorEPC16 does not configure EP2C35 at high temperature
Folks,
I have been debugging this issue where the EPC16 device I use does not configure the EP2C35 (Cyclone II) device - at slightly high temperature. I can make it configure by cooling down both devices using freeze spray. :confused: This is the most fascinating and ridiculous part of the problem - how could the temperature be influencing the basic config cycle?? I am using the Passive Serial mode of configuration. The programming files are proven good. I see the nCONFIG going high followed shortly by nSTATUS and after that ... nothing. The DCLK/DATA0 lines are flatlined (DATA0 continues to remain high and DCLK continues to remain low). Obviously in this case, the CONF_DONE signal does not go high at all. See waveforms below - Ch1 – Yellow – nCONFIG Ch2 – Blue – nSTATUS Ch3 – Purple – CONF_DONE Ch4 – Green – INIT_DONE This is a bad config cycle. http://i41.tinypic.com/23ib0pl.jpg On a good config cycle (same board, freezing cold ICs)... http://i43.tinypic.com/1evt07.jpg I verified the power up sequence - the VCCIO (3.3V) powers up first (t0). The FPGA-VCCINT (1.2V) powers up at (t0 + 69.2ms). The EPC16 is set to have a POR of 100ms. So I am assuming this powers up at (t0 + 100ms). This meets the spec. I have tried 1K & 10K pullups on the INIT_CONF signal with no luck. I am seeing this on 4-5 of 30 boards. On some boards the issue is a lot more aggravated than the others. One board in particular fails at room temperature. Other boards only seem to fail @ 45-55C. I have checked to verify that the EPC16 is revC silicon. Any ideas??14 Replies
Altera_ForumAccording to the waveforms, the EPC16 is simply not starting configuration after nSTATUS is deasserted. So I guess, the problem is related to this device rather than the FPGA. The reason for configuration failure can't be explained from the shown waveforms, I think. But it may be probably caused by other EPS16 signals, e. g. an incorrect terminated TCK.
- Altera_Forum
Could it be a problem in the soldering process?
- Altera_Forum--- Quote Start --- What does the timing of dclk and data0 look like at the fpga? --- Quote End --- During a bad cycle, the DCLK and DATA0 are dead - flatlined. During a good config cycle - they look reasonable enough. I will try to capture a waveform and post it. The CycloneII and EPC device are only a couple of inches apart.
- Altera_Forum
What does the timing of dclk and data0 look like at the fpga?
