Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- What does the timing of dclk and data0 look like at the fpga? --- Quote End --- During a bad cycle, the DCLK and DATA0 are dead - flatlined. During a good config cycle - they look reasonable enough. I will try to capture a waveform and post it. The CycloneII and EPC device are only a couple of inches apart.