Forum Discussion
XQSHEN
Occasional Contributor
Occasional ContributorEP4CE15M9I7N layout guide
Any layout guide for EP4CE15M9I7N for DDR2 routing?
As it's very small pintch 0.5mm, and we need to consider impedance match, it's not easy to route the trace. Any layout guide line?
In the pin...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi XShen1,
Unfortunately, the layout for the EPACE15M9I7N is not available.
The PIN_T7 should be assigned as DQS pin location.
But if you find that the DQS is differential, you can let the Quartus to assign the other pin location during the Fitter compilation.
The DDR2 interface are differential or single ended.
Regards,
Adzim
XQSHENOccasional Contributor
Occasional ContributorI still see below problem.
1) If use single end, at least 2 DQS are needed for 16 bit DDR2. Why only pin T7 is assigned?
2) If use differential, another pin should R7 as pair of T7, but it's already assigned to DQ signal.
