Forum Discussion

Honored Contributor

13 years ago

EP4CE Cyclone configuration timings

I'm coding up a host micro to configure an EP4CE10 in FPP mode. Where do Altera hide the timings, as all I have found so far is that DCLK must be less than 100MHz? In particular: How long do I nee...

Altera_Forum

Honored Contributor

13 years ago

You can find the timing at page 8-36 of the Cyclone IV device handbook - configuration (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf).

Forum Discussion

EP4CE Cyclone configuration timings

Recent Discussions

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

Max10 FPGA Programming with .pof file

Agilex 5 RSU, application image addition fails

MAX10 RSU upgrade succeeds, but device boots Factory image instead of Application

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy