EP4CE Cyclone configuration timings

Question

I'm coding up a host micro to configure an EP4CE10 in FPP mode. Where do Altera hide the timings, as all I have found so far is that DCLK must be less than 100MHz? In particular:

How long do I need to hold nCONFIG low?

How long should I wait for nSTATUS to go high?

How soon after nSTATUS goes high can I apply the first DCLK edge?

altera_forum · Answer

You can find the timing at page 8-36 of the Cyclone IV device handbook - configuration (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf).

Forum Discussion

EP4CE Cyclone configuration timings

1 Reply

Recent Discussions

Operating temperature for 10M08DCF256A7G

Question for LPDDR5 power sharing guideline

Cyclone 10 LP's Extended Industrial parts

Does the Agilex7 M-series support LPDDR5X component?

System PLL of Agliex5 PCIE example design cannot be locked after configuration