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Altera_Forum
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Honored ContributorEP4CE Cyclone configuration timings
I'm coding up a host micro to configure an EP4CE10 in FPP mode. Where do Altera hide the timings, as all I have found so far is that DCLK must be less than 100MHz? In particular:
How long do I need to hold nCONFIG low? How long should I wait for nSTATUS to go high? How soon after nSTATUS goes high can I apply the first DCLK edge?1 Reply
Altera_ForumYou can find the timing at page 8-36 of the Cyclone IV device handbook - configuration (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf).
