Honored Contributor1-are ep2c5t144c8n have fifo ram or internal sram (i want to buffer adc small data fifo) or i need external sram ?
2-are epm240t100c5n have fifo ram or internal sram (i want to buffer adc small data fifo) or i need external sram ? what is internal sram size in both chip if it have
Honored ContributorHi,
for the EP2C5, please refer to the "Cyclone II Device Family Data Sheet", section 2, "Embedded Memory". It has a total of 119,808 bit of internal SRAM. You can use the MegaWizard / IP Catalog to generate standard RAM or FIFO memory entities. Alternatively, you can simply implement a RAM or FIFO in VHDL/Verilog, the synthesis tool will automatically map these to internal SRAM if possible (you might have to rifle through the synthesis and fitter settings to enable this). The EPM240 has no internal SRAM (please refer to the "MAX II Device Handbook", section 1, "Features"). I never worked with that generation of CPLDs, but I assume you can implement a few bits of RAM or FIFO using the logic elements. If you want to know how to implement memory in VHDL, you can e.g. use this as a starting point: http://www.deathbylogic.com/2013/07/vhdl-standard-fifo/ (http://www.deathbylogic.com/2013/07/vhdl-standard-fifo/). Easy with an FPGA, but impractical on a CPLD. Best regards, GooGooCluster
