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Altera_Forum
Honored Contributor
Honored Contributor"end of initialization" reset
Hi everybody, Are there internal power-up reset or "end of initialization" reset signals that can be read to check for start-up reset condition in cyclone FPGA's? Whitebird
Altera_ForumHonored Contributor
Honored ContributorWould the optional INIT_DONE output give you what you need?
Every internal register will be cleared at power up. You could have a register continuously clock in a high data input. When the register output goes high, you will know that the power-up reset phase has ended.
