Enabling series termination on 1.0V and 3.3V IOs in MAX10 FPGA

Well, in that case you would be using those I/Os out of spec.

Most likely they still might work, but you will likely find slower slew rates/timing and/or reduced noise margin.

So if this is a one off design for use at room temperature you will likely find it still works.

But if this is a volume commercial design expected to work over the full device temperature/voltage range, then who knows.

If you do get failures, you can't go back to Intel and complain that their 1.2V I/Os are not working as expected at 1.0V.

You will be on your own at that point.

Your profile says you are an Intel employee, correct?