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Dear all,
Thanks in advance for reading this thread and if possible please comment and advise me to find a suitable solution.
I have built a FPGA based testbed that realizes FPGA-to-FPGA communication for exchanging data and control messages of a network protocol. This transmission is done by means of SMA cables connected to transceivers on the FPGA boards (Stratix IV GT). Because the cables are much shorter compared to cables in the real network, I want to emulate a long propagation delay by delaying the streaming output data in FPGA design. In my understanding, this is something like what the "Avalon-ST delay" IP core in Qsys and the "RAM-based Shift Register" megacore in MegaWizard Manager do. But these two cores provide a small number of cycles (maximum is 256 clk cycles) for which the streaming output is delayed.
If you know the other IP core that supports a very large number of clock in delay, or you have a better solution for my issue, please advise. I need to have up to 312500 clock cycles of delay with my working clock (156.25Mhz), i.e., 2 milliseconds.
Best regard,
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If your data stream is 1 bit wide then you can use some 34 blocks of M9Ks for 312500 sample storage. if it is much wider then you will need external ram (e.g. sdram). Internal fpga ram based shift register will impose a minimum limit on tap distance of 3 stages or so.
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