Emulated LVDS outputs and Quartus pin planner

Good afternoon Sree,

I'll try to describe the problem once again:

I've used to write the code at ModelSim before loading it Quartus.

It is very important at ModelSim to describe all output ports: positive and negative.

Then I'm importing all the project into Quartus II.

When I'm trying with Pin Planner to connect an output ports (negative and positive) to matching pins (emulated LVDS format),

then Quartus II splits outputs (Negative and Positive ports of the project) into Negative and positive node each.

For example: I have to get out from FPGA with 4 emulated LVDS pairs of signals : CLK_N(0 to 3) and CLK_P(0 to 3).

So, there are 8 output ports CLK_N(0 to 3) and CLK_P(0 to 3) at ModelSim Top level entity.

When I'm trying to connect ModelSim Top Level Ports with emulated LVDS dedicated pins (of FPGA) with Pin Planner ,then

Quartus-II splits CLK_N(0) to CLK_N(0) and CLK_N(n)(0) ,

CLK_P(0) to CLK_P(0) and CLK_P(n)(0), etc.

Therefore, the question is:

1)How can user connect an existing output ports to the emulated LVDS dedicated pins by Pin Planner without splitting?

If I'm writing at ModelSim Top level entity only CLK_P(0 to 3) (without CLK_N(0 to 3) 'then I can connect these ports to emulated LVDS dedicated pins without splitting.

The Quartus-II will complete negative "Node Name" automatically.

But ModelSim entity includes only half of the needed ports (positive ones).

Therefore the question is:

How can I connect Quartus generated Node names with ModelSim Top entity ports?